The present invention relates to semiconductor technology. Specifically, embodiments of the invention are directed to an electrically programmable fuse (eFuse) cell array and memory device.
In a conventional cell array of electrically programmable fuses (referred to as “eFuse” hereinafter), an eFuse unit includes an eFuse cell and a switch. In a write operation, for example, a relatively high current will flow through the eFuse to burn the eFuse for writing information to the eFuse unit. Thus, a write operation may be referred to as a fusing operation, and a write current is also referred to as a fusing current.
Since the write current is relatively high, a switch of an eFuse unit, e.g., an NMOS transistor, will be relatively large and occupies most of the area of the eFuse unit, e.g., 80% of the eFuse unit area. Furthermore, in a read operation, the current flowing through the eFuse unit is constrained by the maximum read current and the read duration, that limits the number of read operations.
FIG. 1 is a schematic diagram of a 1R2T circuit of an eFuse unit, as known in the prior art. The eFuse unit includes an electrically programmable fuse 11 having a terminal connected to a write NMOS transistor 12 and a read NMOS transistor 13. In a read operation, write NMOS transistor 12 is turned off, and read NMOS transistor 13 is turned on. In a write operation, both write NMOS transistor 12 and read NMOS transistor 13 are turned on. Since the read current is very small, such as equal to about 1% of the write current, so that the read NMOS transistor can be very small. Because the read current is reduced, it is possible to significantly increase the number of read operations. However, such structure of the eFuse unit does not significantly reduce the area comparing with the 1R1T circuit of a conventional eFuse unit, the problem of a relatively large area remains.
Thus, there is a need for a novel eFuse structure and method of manufacturing the same.